Datasheet: 
74LVC164255 16-bit dual supply translating transceiver; 3-state
Package: SOT370-1 SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm
General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. nDIR (active HIGH) enables data from nA ports to nB ports. nDIR (active LOW) enables data from nB ports to nA ports. The output enable inputs (1OE and 2OE), when HIGH, disable both nA and nB ports by placing them in a high-impedance OFF-state. Pins nA, nOE and nDIR are referenced to VCC(A) and pins nB are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode).
Features
- 5 V tolerant inputs/outputs for interfacing with 5 V logic
- Wide supply voltage range:
- 3 V port (VCC(A)): 1.5 V to 3.6 V
- 5 V port (VCC(B)): 1.5 V to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Control inputs voltage range from 2.7 V to 5.5 V
- Inputs accept voltages up to 5.5 V
- High-impedance outputs when VCC(A) or VCC(B) = 0 V
- Complies with JEDEC standard JESD8-B/JESD36
- ESD protection:
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Specified from -40 Cel to +85 Cel and -40 Cel to +125 Cel